This invention relates generally to scaling of analog input signals and in particular to scaling both bipolar and unipolar input signals to the dynamic range of an ADC prior to acquisition and conversion, and is more particularly directed toward sampling an analog input signal through high-voltage transmission gates onto a selected combination of sampling capacitors to program the input range of a SAR ADC.
Multi-input, wide dynamic range bipolar and unipolar successive approximation analog-to-digital converters (ADCs) have traditionally used resistor divider networks at the analog input to scale the input signal to the dynamic range of the converter before acquisition and conversion can take place. This method of attenuating the input signal prior to conversion by the ADC has been used very successfully in the past. However, it has a number of distinct disadvantages.
First of all, in the traditional resistor divider approach the analog input source always sees a resistive load to ground or some reference voltage. The source must be able to drive this load. Second, the resistor divider network consumes power both from the internal reference and from the analog input source. The third problem is that this prior art technique does not allow the user an easy method for programming the allowed analog input range. A fourth disadvantage is the fact that the size of the input resistors will limit the full power bandwidth of the converter.
The nodes of the resistor network that form the resistor divider can be made accessible to the user via pins on an integrated circuit (IC). The user then configures the resistor divider network via hardware connections to suit the analog input range required. However, if the user wishes to change the range, then the hardware has to be re-wired.
Consequently, a need arises for an analog input voltage scaling technique that is easily adaptable to integrated circuit applications, does not require the input signal to drive a resistive load to ground, minimizes power consumption, and is easily programmable in the event that the allowed analog input voltage range requires alteration.
These needs and others are satisfied by the programmable input voltage range system and methodology of the present invention, in which a split gate oxide process allows the use of high voltage (xc2x115 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto the sampling capacitor without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitor, the analog input can be scaled or attenuated to suit the dynamic range of the SAR (successive approximation register) ADC itself.
In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in the SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range. Once the analog input signal has been attenuated to match the allowed dynamic range of the SAR converter, traditional SAR techniques can be used to convert the input signal to a digital word.
In this manner, many of the problems of traditional methods are overcome. The analog source sees a capacitive load, not a resistive load to groundxe2x80x94therefore, no DC power is required from the source. Second, no additional power is consumed in biasing a resistor divider network. And last of all, by selecting which bits of the capacitive redistribution DAC or separate sampling array to sample onto, one can program, through software, the analog input range.
In accordance with one aspect of the present invention, a programmable input voltage range analog-to-digital converter comprises a successive approximation analog-to-digital converter (SAR ADC) having a characteristic dynamic range, and an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC. In one form of the invention, the input voltage scaling network is a capacitive redistribution digital-to-analog converter forming a part of the SAR ADC.
A network of high voltage sampling switches may be interposed between the input voltage and the input voltage scaling network, such that range decoder logic selects one or more elements of the input voltage scaling network on which the input voltage is sampled. The input voltage range may be bipolar.
In another form of the invention, a network of low-voltage to high-voltage level shifters couples control signals to the high voltage sampling switches. Preferably, the range decoder logic is responsive to a range selection control word written into an associated range register. The range register may be programmable via a digital communication interface. It is preferred that the digital communication interface be a serial, bi-directional communication interface to accommodate both programming of the range register by a user, and read-back of the range register contents for verification, as well as for programming other functionality of the SAR ADC itself.
In accordance with another aspect of the present invention, a SAR ADC comprises a capacitive redistribution digital-to-analog converter (CapDAC) having an output coupled to a comparator, SAR logic that controls iterative sampling of a SAR ADC input signal and monitors the output of the comparator, an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC, a network of high voltage sampling switches interposed between the input voltage and the input voltage scaling network, such that the input voltage is selectively sampled onto one or more of the sampling capacitors, range decoder logic that controls the network of high voltage sampling switches to select one or more of the sampling capacitors, and a range register to which a range selection control word is written, the range decoder logic being responsive to the range selection control word.
The CapDAC may form at least a part of the input voltage scaling network, and the input voltage may be sampled onto one or more selected sampling capacitors of the CapDAC to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC. In the alternative, the input voltage scaling network may comprise a network of sampling capacitors independent of the CapDAC array.